An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scalingC. H. Diaz, Hun-Jan Tao, Yao-Ching Ku, A. Yen, K. YoungIEEE Electron Device Letters2001This letter introduces an analytical model to represent line-edge roughness (LER) effects on both off-state leakage and drive current for sub-100-nm devices. The model partitions a given device into… (More)