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Gate-induced-drain-leakage (GIDL) current in 45 nm state-of-the-art MOSFETs is characterized in detail. For the current technology node with a 1.2 V power-supply voltage, the GIDL current is found to increase in MOSFETs with higher channel-doping levels. In contrast to the classical GIDL current generated in the gate-to-drain overlap region, the observed(More)
This paper reviews progress and current critical issues with respect to the integration of germanium (Ge) surface-channel MOSFET devices as well as strained-Ge buried-channel MOSFET structures. The device design and scalability of strained-Ge buried-channel MOSFETs are discussed on the basis of our recent results. CMOS-compatible integration approaches of(More)
This paper reviews the current critical issues on the fabrication of Ge surface channel MOSFET devices. Compared with surface channel Ge MOSFETs, strained Ge buried channel structures can be integrated with fewer processing challenges to achieve significantly enhanced hole mobility and an improved electron mobility. The device design and scalability of the(More)
Conventional scaling is no longer effective to continue device performance trend because of technological difficulties in the scaling of key device parameters. In this paper, we discuss device scaling options beyond convention device structures. We discuss ultrathin body silicon on insulator (UTSOI) MOSFET and FinFET structures for improved electrostatic.(More)
Conventional scaling is no longer effective to continue device performance trend because of technological difficulties in the scaling of key device parameters. In this paper, the authors discussed device scaling options beyond convention device structures. Recent progress in advanced gate stack, ultrathin body silicon on insulator (UTSOI) MOSFET and FinFET(More)
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