Huicai Zhong

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A high performance 65 nm SOI CMOS technology is presented featuring 35 nm gate length, 1.05 nm gate oxide, performance enhancement from dual stress nitride liners (DSL), and 10 wiring levels with low-k dielectric offered in the first 8 levels. DSL enhancement is shown to scale well to 65 nm with larger enhancement seen than at 90 nm design rules. A high(More)
A reliable antifuse (AF) one-time-programmable (OTP) cell and its sensing plus programming circuits for postpackage repair of dynamic random access memory (DRAM) are presented. The OTP cell was fabricated without any process modifications by utilizing destructive breakdown of thin gate oxide of nMOS capacitor as storage. The measurement results of OTP array(More)
Reverse halo implantation (RHI), for the first time, is introduced and used to fabricate MOSFETs. It was demonstrated that RHI can dramatically improve short-channel effect, which can be used to enhance MOSFET performance, improve process control, or reduce stand-by power consumption. Implantation damage of RHI to gate oxide is negligible. The method of RHI(More)
Dramatic EOT shrinking and Vfb increasing were observed when implanting Ga ions into high-k/metal-gate stack. Experiments with different gate-metal thickness, dosages, ion types, and post gate-etch anneal conditions were studied. Elastic dipole theory, for the first time, is proposed and ab-initio simulations were conducted to explain the unexpected trends.(More)
A novel methodology to statistically analyze the statistics on small device performance is presented for the first time. To verify the accuracy of analysis and modeling, TCAD simulation is used to mimic possible process-induced and random fluctuations. The proposed approach precisely decouples various process dependency of the device electric behavior and(More)
In this letter, a novel self-aligned CMOS-compatible method for the fabrication of gate-all-around silicon nanowire MOSFETs (GAA SNWFETs) on bulk substrate has been proposed. The fabricated SNWFET featuring 33-nm gate length and 7-nm diameter shows the highest driving current (<i>I</i><sub>on</sub> = 2500 &#x03BC;A/&#x03BC;m at <i>V</i><sub>ds</sub> =(More)
We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with a metal gate length of 25 nm and an effective channel length less than 20 nm. The SPW features a retrograde doping profile in vertical direction and a doping profile self-aligned with drain/extension in lateral direction. A novel process, called(More)
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