Hui-Wen Tsai

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A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide overstress problem in low-voltage CMOS process. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply(More)
A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide reliability problem in low-voltage CMOS process. The four-phase clocks were used to control the charge-transfer devices turning on and turning off alternately to suppress the return-back leakage current. A test chip has been implemented(More)
Phalaenopsis is a winter-blooming orchid genus commonly cultivated in tropical Asian countries. Because orchids are one of the most economically important flower crops in Taiwan, it is crucial to understand their response to cold and other abiotic stresses. The present study focused on gene regulation of P. aphrodite in response to abiotic stress, mainly(More)
A new 2xVDD-tolerant I/O buffer circuit, realized with only 1xVDD devices in nanoscale CMOS technology, to prevent transistors against gate-oxide reliability and hotcarrier degradation is proposed. The new proposed 2xVDDtolerant I/O buffer has been implemented in a 130-nm CMOS process to serve a 2.5-V/1.2-V mixed-voltage interface without using the(More)
A new 2xVDD-tolerant mixed-voltage I/O buffer circuit, realized with only 1xVDD devices in deep-submicron CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2xVDD-tolerant I/O buffer has been designed and fabricated in a 0.13-lm CMOS process with only 1.2-V devices to serve a(More)
A circuit solution to generate compensation current that can decrease the perturbation induced by the external latchup trigger was proposed. The robustness against latchup can be improved by supporting compensation current at the pad under latch-up current test. By inserting additional junctions to sense the latchup trigger current, the injected latchup(More)
A concept of active guard ring and its corresponding circuit solution to enhance the latch-up immunity of integrated circuits (IC) are proposed and verified in a 0.6-um 5-V CMOS process. By detecting the over-shooting/under-shooting trigger current during latchup current test (I-test), some compensation current generated from on-chip ESD PMOS or NMOS(More)
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