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SUMMARY This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture. With the proposed architecture on the Altera Stratix FPGA, two PPR implementations achieve 6.45 Gbps throughput and 12.78 Gbps throughput, respectively. Compared with the unrolling implementation that achieves a(More)
The first implementation of a new programmable logic device using LUT(Look-Up Table) cascade architecture is developed in 0.35um CMOS logic process. Eight 64Kb asynchronous SRAMs are simply connected to form an LUT cascade with a few additional circuits. Benchmark results show that it has a competitive performance to FPGAs. 1. Introduction RAMs and PLAs(More)
This paper addresses a pipelined partial rolling (PPR) architecture for the AES encryption. The key technique is the PPR architecture, which is suitable for FPGA implementation. Using the proposed architecture on the Altera Stratix EP1S20F780C5 FPGA, the AES-4SM achieves a throughput of 5.61 Gbps by using 20 M4Ks, and the AES-8SM achieves a throughput of(More)
Keywords: Short-term hydrothermal generation scheduling Differential evolution algorithm Adaptive Chaotic local search Constraint handle a b s t r a c t The short-term hydrothermal generation scheduling (SHGS) is a complicated nonlinear optimization problem with a set of operational and hydraulic constraints. A new approach is presented in this paper for(More)