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Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compilation tools are essential to their success. In this paper, we present a modulo scheduling algorithm to exploit loop-level parallelism for coarse-grained reconfigurable architectures. This algorithm is a key part of our Dynamically(More)
Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compiling tools are essential to their success. In this paper, we present a retargetable compiler for a family of coarse-grained reconfigurable architectures. Several key issues are addressed. Program analysis and transformation prepare(More)
In this article, we propose a global assignment theory for encoding state graph transformations. A constraint satisfaction framework is proposed that can guarantee necessary and sufficient conditions for a state graph assignment to result in a transformed state graph that is free of critical races. Performing transformations at the state graph level has the(More)
The joint effects of IQ imbalance and phase noise on OFDM systems are analyzed, and a compensation scheme is proposed to improve the system performance. The scheme consists of a joint channel estimation algorithm and a joint data symbol estimation algorithm. In the proposed channel estimation algorithm, the channel coefficients are jointly estimated with(More)
Two major technical challenges in the design of future broadband wireless networks are the impairments of the propagation channel and the need for spectral efficiency. To mitigate the channel impairments, orthogonal frequency division multiplexing (OFDM) can be used, which transforms a frequency-selective channel in a set of frequency-flat channels. On the(More)
In this paper, we present some strategies that are capable of reducing the required memory sizes and power consumption for a large class of data-intensive multimedia applications. This class consists of static control programs with large multi-dimensional arrays and (piece-wise) aane storage and execution order. These strategies are equally well suited for(More)
In this paper, we discuss a <italic>control-flow transformation</italic> called <italic>loop folding</italic>, during the scheduling of register-transfer code for DSP-systems. Loop folding is functionally equivalent to data-path <italic>pipelining</italic>. An iterative loop-folding procedure, implemented in the CATHEDRAL II compiler, is presented. This(More)