Hubert Enichlmair

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Our physics-based HCD model has been validated using scaled CMOS transistors in our previous work. In this work we apply this model for the first time to a high-voltage nLDMOS device. For the calculation of the degrading behaviour the Boltzmann transport equation solver ViennaSHE is used which also requires high quality adaptive meshing. We discuss the(More)
Integration of low voltage analog and logic circuits as well as high-voltage (HV) devices for operation at greater than 5V enables Smart Power ICs used in almost any system that contains electronics. HVCMOS (High-Voltage CMOS) technologies offer much lower process cost, if compared to BCD technologies, they enable multiple HV levels on a single chip, and(More)
At elevated temperatures, pMOS transistors show a considerable drift in fundamental device parameters such as the threshold voltage when a large negative bias is applied. This phenomenon, known as negative bias temperature instability, is regarded as one of the most important reliability concerns in highly scaled pMOS transistors. Modeling efforts date back(More)
We propose a physics-based model for hot-carrier degradation (HCD), which is able to represent HCD observed in n-channel high-voltage MOSFETs with different channel length with a single set of physical parameters. Our approach considers not only damage produced by channel electrons but also by secondary generated channel holes. Although the contribution of(More)
We demonstrate “on the fly” electron spin resonance ESR in which the defect generation process in the negative bias temperature instability NBTI can be observed without recovery contamination. Elevated temperature and modest negative gate bias generates ESR spectra due to E center defects. The NBTI generated E center spectrum disappears upon stress(More)
We refine our approach for hot-carrier degradation modeling based on a thorough evaluation of the carrier energy distribution by means of a full-band Monte–Carlo simulator. The model is extended to describe the linear current degradation over a wide range of operation conditions. For this purpose we employ two types of interface states, either created by(More)
We propose and verify a model for hot carrier degradation based on the exhaustive evaluation of the energy distribution function for charge carriers in the channel by means of a full-band Monte-Carlo device simulator. This approach allows us to capture the interplay between “hot” and “colder” electrons and their contribution to(More)
We present a thorough analysis of physics-based hot-carrier degradation (HCD) models. We discuss the main features of HCD such as its strong localization at the drain side of the device, the weakening of the degradation at higher temperatures, and the change of the worst-case condition in small devices. The first feature is related to “hot” carriers, while(More)
We have analyzed the worst-case conditions of hot-carrier induced degradation for high-voltage n- and p-MOSFETs with our model. This model is based on the evaluation of the carrier distribution function along the Si/SiO<inf>2</inf> interface, i.e. on thorough consideration of carrier transport. The distribution function obtained by means of a full-band(More)
We propose two different approaches to describe carrier transport in n-laterally diffused MOS (nLDMOS) transistor and use the calculated carrier energy distribution as an input for our physical hot-carrier degradation (HCD) model. The first version relies on the solution of the Boltzmann transport equation using the spherical harmonics expansion method,(More)