Hsin-Chou Chi

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Crossbars are key components of communication switches used to construct multiprocessor interconnection networks. Multi-queue input buffers have been shown to lead to high performance in such networks by allowing packets at an input port to be processed in non-FIFO order. Symmetric crossbar arbiters efficiently resolve conflicting requests in switches with(More)
High-throughput low-latency interconnection networks are suitable for workstation clusters. An interconnection network can be constructed in different topologies. Typically, interconnection networks with regular topologies, such as mesh, torus, and hypercube, are less scalable for workstation clusters than those with irregular topologies. There have been(More)
Network-on-chip (NoC) architectures have been recently proposed as the communication framework for large-scale chips. The design of the routing system for the packet-switched on-chip network is one of the critical issues for the success of NoC architectures, especially when there are faulty components in the network. In this paper, we present a routing(More)
Network-on-chip (NoC) architectures provide a high-performance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput, and hence are suitable for NoC architectures with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application(More)
Locating the scan chain fault is a critical step for IC manufacturers to analyze failure for yield improvement. In this paper, we propose a diagnosis scheme to locate the single stuck-at fault in scan chains. Our diagnosis scheme is an improved design to a previously proposed scheme which can diagnose the output of each cell flip-flop in the scan chain.(More)