Hsien-Chie Cheng

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To prevent potential yield loss, achieve TSV with higher aspect ratio, improve the bonding reliability, and reduce the process cost, a clamped through silicon via (C-TSV) interconnection for stacked chip bonding is proposed and developed in this paper. The metal cap on pad design can not only be a bonding layer for other stacked die on it, but also performs(More)
The minimum system temperature design of MCMs containing a number of chips of equal power for design in natural convection is pursued through the optimal thermal placement of chips. For dealing with the thermal optimization problems, a simple but effective thermal design methodology that integrates a modified force-directed (FD) algorithm and a finite(More)
As the strained engineering technology of metal-oxide-semiconductor field effect transistors (MOSFET) is scaled beyond the 22 nm node critical dimension, shallow trench isolation (STI) becomes one of the most important resolutions for isolate devices to enhance the carrier mobility of advanced transistors. Several key design factors of n-type MOSFET(More)
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