Hsien-Chie Cheng

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To prevent potential yield loss, achieve TSV with higher aspect ratio, improve the bonding reliability, and reduce the process cost, a clamped through silicon via (C-TSV) interconnection for stacked chip bonding is proposed and developed in this paper. The metal cap on pad design can not only be a bonding layer for other stacked die on it, but also performs(More)
In this study, a prototype of web-based distributed problem-solving environment (W-DPSE) is presented to facilitate computer aided engineering (CAE) technologies. This system provides an effective approach to distributed modeling and simulation, and in addition, to support networked collaboration such that scientists around the world could interactively,(More)
The minimum system temperature design of MCMs containing a number of chips of equal power for design in natural convection is pursued through the optimal thermal placement of chips. For dealing with the thermal optimization problems, a simple but effective thermal design methodology that integrates a modified force-directed (FD) algorithm and a finite(More)
As microelectronic packaging industry grows explosively, high I/O density interconnects and reliable packaging design are recognized as the main concern of the IC packaging industry. Hence, in this investigation, a novel type of anisotropic conductive film (ACF) composed of cobalt nanowires and polymer was developed and used in place of conventional solder(More)
As the strained engineering technology of metal-oxide-semiconductor field effect transistors (MOSFET) is scaled beyond the 22 nm node critical dimension, shallow trench isolation (STI) becomes one of the most important resolutions for isolate devices to enhance the carrier mobility of advanced transistors. Several key design factors of n-type MOSFET(More)
Article history: Received 24 August 2015 Received in revised form 10 December 2015 Accepted 18 December 2015 Available online 30 December 2015 The study aims at evaluation of the steady-state heat dissipation capability of a high-density through silicon via (TSV)-based three-dimensional (3D) IC packaging technology (briefly termed 3D TSV IC packaging)(More)