Hsiao-Ping Lin

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System-on-chip (SOC) design methodology is becomingthe trend in the IC industry. Integrating reusable coresfrom multiple sources is essential in SOC design, and differentdesign-for-testability methodologies are usually requiredfor testing different cores. Another issue is test integration.The purpose of this paper is to present a hierarchicaltest scheme for(More)
Embedded memory test and diagnosis is becoming an important issue in system-on-chip (SOC) development. Direct access of the memory cores from the limited number of I/O pins is usually not feasible. Built-in self-diagnosis (BISD), which include built-in self-test (BIST), is rapidly becoming the most acceptable solution. We propose a BISD design and a fault(More)
In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure(More)
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