Hsiao-Pin Su

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In a hardware emulator consisting of multiple fieldprogrammable gate arrays (FPGA’s), the utilization of the FPGA logic resource is usually very low due to the limitation on the number of I/O pins. Virtual wire technology not only increases the inter-FPGA communication capability, but it also increases the logic resource utilization by means of time(More)
Retiming relocates registers in a circuit to shorten the clock cycle time. In deep sub-micron era, conventional pre-layout retiming cannot work properly because of dominant interconnection delay that is not available before layout. Although some retiming algorithms incorporating interconnection delay have been proposed, layout information is still not(More)
In this paper, we present a complete chip design method which incorporates a soft-macro resynthesis method in interaction with chip oorplanning for area and timing improvements. We develop a timing-driven design ow to exploit the interaction between HDL synthesis and physical design tasks. During each design iteration, we resynthesize soft macros with(More)
<italic>In this paper, we present a performance-driven soft-macro clustering and placement method which preserves HDL design hierarchy to guide the soft-macro placement process. We also present a complete chip design methodology by integrating the proposed method and a set of commercial EDA tools. Experiments on three industrial designs ranging from 75K to(More)
In this paper, we present a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floorplanning for area and timing improvements. We present a performance-driven soft-macro clustering and placement method which preserves hardware descriptive language (HDL) design hierarchy to guide the(More)
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