Hsiang-Hung Chang

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A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS image sensor is then stacked with analog to digital(More)
The paper describes the newly development technology of 3D stacking packaging by introducing laser-drilled through silicon interconnect (LTSI). Compared to the recently abundant researches of 3D chip-to-wafer or wafer-to-wafer stacking, it demonstrated a more reliable and practical process flow to achieve the 3D stacking technology. The investigation of(More)
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