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Locating the scan chain fault is a critical step for IC manufacturers to analyze failure for yield improvement. In this paper, we propose a diagnosis scheme to locate the single stuck-at fault in scan chains. Our diagnosis scheme is an improved design to a previously proposed scheme which can diagnose the output of each cell flip-flop in the scan chain.(More)
As chip complexity keeps increasing in system-on-chip (SoC), the on-chip interconnect has become a critical issue for large-scale chip design. It has been proposed that the packet-switched network exchanging messages between intellectual property (IP) cores is a viable solution for the SoC interconnect problem. The design of the router in such network on(More)
System-on-a-chip (SoC) as a platform for system integration has been used extensively in modern VLSI design. The IEEE P1500 has been proposed as a standard for the challenging SoC testing problem. In order to improve the correctness of SoC testing, the IEEE P1500 hardware itself should be tested and diagnosed first before using it. This paper proposes an(More)
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