Houle Gan

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Many prior works have discussed the power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the early stage of a development cycle, designers have more flexibility to improve the design quality. However, there are several fundamental challenges at early-stage when design(More)
This paper proposes a fast and high-capacity electromagnetic solution, time-domain layered finite element reduction recovery (LAFE-RR) method, for high-frequency modeling and simulation of large-scale on-chip circuits. This method rigorously reduces the matrix of a multilayer system to that of a single-layer one regardless of the original problem size. More(More)
Power integrity has become increasingly important for sub-32nm designs. Many prior works have discussed power grid design and optimization in the post-layout stage, when design change is inevitably expensive and difficult. In contrast, during the early stage of a development cycle, designers have more flexibility to improve the design quality. However,(More)
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