Hossein Sarbishaei

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As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The(More)
Impact of ESD protection devices on circuit operation is very important in gigahertz applications. In this paper, the impact of different ESD protection methodologies on CML drivers is discussed. ESD protection is provided using MOSFET and SCR devices. Study of the interaction between driver and ESD protection circuit shows that jitter is very sensitive to(More)
In this paper we designed an ESD protected CML driver for 8.5Gbps data rate. ESD protection for this circuit is provided with DSCR. A detailed analysis is done on the impact of ESD protection on performance of the driver. It is shown that DSCR offers up to 2.7kV HBM protection with very small impact on performance of the driver.
As technology feature size is reduced, ESD becomes one of the dominant failure modes due to the lower gate oxide breakdown voltage. Also, the holding voltage of LVTSCR devices is reduced with operating temperature increase. As a result, during stress testing (burn-in), the risk of latch-up in LVTSCR is extremely high. In this paper, a new latch-up free(More)
The impact of CMOS technology scaling on the second breakdown of ESD protection devices has been investigated using 2-D simulations and analytical calculations. It is shown that the second breakdown trigger current (It2) can not be reliably used as an ESD robustness criterion in sub-0.18 um ESD protection devices. When a technology feature size is reduced,(More)
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