Hoon-Jae Ki

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This paper presents a high speed, low power 8-tap digital FIR filter for PRML disk-drive read channels. Enhancements on power consumption and speed are achieved by adopting the row compression scheme and proposed conditional carry selection method. The 8-tap digital FIR filter has been fabricated by 0.8um CMOS technology and occupied by 3.9mm×1.5mm.(More)
This paper describes a new pass-transistor logic family, named PPL(Push-pull Pass transistor Logic), for low voltage and low power which restores outputs by the push-pull operation. Using PPL circuits, 40-stage full adder chain and 8-bit multiplier are designed and fabricated in a 0.8¿m CMOS process technology. PPL achieves 36.4ns delay with the power(More)
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