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The Y-architecture for on-chip interconnect is based on pervasiveuse of 0-, 120-, and 240-degree oriented semi-global and globalwiring. Its use of three uniform directions exploits on-chip routingresources more efficiently than traditional Manhattan wiring architecture.This paper gives in-depth analysis of deployment issues associatedwith the(More)
Floorplan representation is a fundamental issue in designing a floorplanning algorithm. In this paper, we first present a twin binary trees structure for mosaic floorplans. It is a nonredundant representation. We then derive the exact number of configurations for mosaic floorplans and slicing floorplans. Finally, the relationships between various(More)
Mesh architectures are used for distributing critical global signals on a chip such as clock and power/ground. The inherent redundancy created by loops present in the mesh smooths out undesirable variations between signal nodes spatially distributed over the chip. However, one outstanding problem with mesh architectures is the difficulty in analyzing them(More)
As semiconductor process technologies shrink, interconnect planning presents ever-greater challenges to designers. In this paper, we analyze, evaluate and compare various metrics with optimized wire configurations in the contexts of different design criteria: delay minimization, delay-power minimization and delay-power minimization. We show how various(More)
This paper evaluates and compares different clock architectures such as mesh, tree and their hybrids, on several industrial designs. The goal of our study is to gain a quantitative understanding of engineering trade-offs between different architectures with respect to clock skew, latency, timing uncertainty, and power. This understanding will lead to(More)
Doping is a widely applied technological process in materials science that involves incorporating atoms or ions of appropriate elements into host lattices to yield hybrid materials with desirable properties and functions. For nanocrystalline materials, doping is of fundamental importance in stabilizing a specific crystallographic phase, modifying electronic(More)
λ-geometry routing has recently received much attention due to the potential for reduced interconnect length in comparison to today’s prevalent Manhattan routing. An accurate cost-benefit analysis of λ-geometry routing is impossible without good estimation of the wirelength reduction expected when switching from Manhattan to λ-geometry routing. However, in(More)
In this paper, we investigate the effect of multilevel network for clock skew. We first define the simplified RC circuit model of a hybrid clock mesh/tree structure. The skew reduction effect of shunt segment contributed by the mesh is derived analytically from the simplified model. The result indicates that the skew decreases proportionally to the(More)
We devised an efficient and accurate estimation of the rectilinear Steiner minimal tree (SMT), which is an essential building block for on-line and posteriori interconnect prediction. We proposed a new rectilinear Steiner tree generator, Refined Single Trunk Tree (RST-T). Compared with traditional minimal spanning tree based Steiner tree heuristics, RST-T(More)
Solanum lycopersicum and Solanum habrochaites are closely related plant species; however, their cold tolerance capacities are different. The wild species S. habrochaites is more cold tolerant than the cultivated species S. lycopersicum. The transcriptomes of S. lycopersicum and S. habrochaites leaf tissues under cold stress were studied using Illumina(More)