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Word embeddings encode semantic meanings of words into low-dimension word vectors. In most word embeddings, one cannot interpret the meanings of specific dimensions of those word vectors. Nonnegative matrix factorization (NMF) has been proposed to learn interpretable word embeddings via non-negative constraints. However, NMF methods suffer from scale and(More)
The performance of deep neural networks is well-known to be sensitive to the setting of their hyperparameters. Recent advances in reverse-mode automatic differentiation allow for optimizing hyperparameters with gradients. The standard way of computing these gradients involves a forward and backward pass of computations. However, the backward pass usually(More)
In this paper, a dynamic relocation cache scheme is proposed for low power processor. Based on an energy consumption function of cache system, which mapping the cache energy consumption problem to a binary ILP (Integer Linear Programming) problem, this dynamic relocation cache scheme map the static code to a dynamic location through an address mapping(More)
In this paper, an innovative method to analyze the software specifications by using a model based on the Markov Chain is proposed. It is well known that all kinds of software are executed via the instruction set of the processor. Since the instruction set can be classified and divided into a series of finite state (i.e. the finite-state machine), it is(More)
The back-propagation (BP) algorithm has been considered the de-facto method for training deep neural networks. It back-propagates errors from the output layer to the hidden layers in an exact manner using the transpose of the feedforward weights. However, it has been argued that this is not biologically plausible because back-propagating error signals with(More)
Because the spatial and temporal locality of program codes, compiler could use heuristics and profile guided prediction to relocate the output of program codes to reduce the cache confliction. In this paper, for improving the average accessing time of memory subsystem by raising the cache hit rate, hybrid compiler assisted prediction and relocation(More)
In this paper, two different architectures of the iSLIP scheduling algorithm are implemented by hardware, and the delay limitation of this algorithm is indicated by comparing their performances. Then a matrix model is proposed for analyzing the reason of delay limitation, and the conclusion is that the pointer conflict causes the large area and delay in(More)
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