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Context-based adaptive variable length coding (CAVLC) is a new and important feature of the H.264/AVC. Based on analysis and modification of the conventional run-length coding architecture, a novel high efficiency VLSI architecture for H.264/AVC CAVLC encoding is presented in this paper. An approach called arithmetic table structure is exploited to replace(More)
A high efficiency memory controller of Synchronous DRAM is proposed to improve memory bandwidth in H.264 HDTV encoder. The feature of SDRAM and memory access pattern of H. 264/AVC encoder is analyzed for suitable controller architecture designing. A new data arrangement in SDRAM has been used to improve bus efficiency by reducing the overhead cycle of(More)
FPGA and ASIC are suitable platforms for high definition video encoder implementation. Efficient video encoder VLSI architecture design suffers from several challenges and multiple target performance trade-off. Algorithm and hardware architecture are supposed to be jointly designed for multiple target performance trade-off. How to evaluate the performance,(More)
Summary form only given. Huge SDRAM memory access bandwidth is the performance bottleneck for high definition video coding. Lossless image compression is efficient method to solve this problem. Image pixels are compressed before writing into SDRAM and decompressed after reading out from SDRAM. This work proposes a hardware-oriented lossless image(More)
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