Hongjoong Shin

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In this paper, we introduce a novel substrate noise estimation technique during early floorplanning, based on the concept of Block Preference Directed Graph (BPDG) and the classic Sequence Pair (SP) floorplan representation. Given a set of analog and digital blocks, the BPDG is constructed based on their inherent noise characteristics to capture their(More)
Loopback testing of Mixed-signal SOCs provides a low-cost test solution, but suffers from fault masking, resulting in serious yield loss and low test accuracy. This paper presents an efficient loopback test methodology which enables individual characterization of dynamic performance of Devices Under Test (DUTs) in loopback mode. DUTs are loop-backed(More)
Accurate generation of circuit specifications from test signatures is a difficult problem, since analytical expressions cannot precisely describe the nonlinear relationships between signatures and specification. In addition, it is difficult to precisely control physical factors in Built-in Self-test (BIST) circuitry, which can cause errors in the(More)
Signatures used in low-cost schemes for testing analog and mixed-signal circuits do not directly represent or characterize the behavior of the device-under-test (DUT), since the lossy compression or complicated mathematical relations used can result in the loss of physical performance information. We develop a novel scheme where the signature is generated(More)
This paper presents a new analog BIST scheme using a slope detection technique. In test mode, a circuit under test (CUT) is stimulated with a periodic rectangular pulse generated from a Linear Feed-Back Shift Register (LFSR) and a periodic invariant response is generated. The width of the pulse is a BIST parameter to allow a trade-off between test time and(More)
This paper presents a new low-cost fault diagnosis technique based on Built-in Self Test (BIST). The method enables rapid and accurate identification of weak spots in a design and potential problems in the manufacturing process, thereby leading to a significant reduction in time-tomarket. Fault diagnosis is accelerated with available onchip BIST which can(More)