Hong-June Park

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This paper presents a 100 kS/s, 1.3 μW, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The effects of gain, noise, and offset are also investigated by detailed analysis which(More)
An all-digital 90deg phase-shift DLL is proposed for 1.6 Gbps DDR interface by using a loop-embedded DCC and a binary phase detector with the lock range extended to 0~4pi radians. The DCC has a small delay and the fixed rising-edge property for loop-embedding. The chip fabricated with a 0.13 um CMOS process gives the DLL data rate of 667 Mbps~1.6 Gbps and(More)
A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO. The coarse block consists of two ladder-shaped coarse delay chains. The delay of the first one is an odd(More)
Ultrasound imaging is widely used for medical diagnosis, because it is harmless to the human body and has real-time processing capability. Usually the focusing (beamforming) operation is performed for both TX and RX. The RX focusing is performed by an RX beamformer [1-5], which consists of delay elements and adders. Nowadays, digital beamformers (DBF) are(More)
A 3Gbit/s/pin 8b parallel 4-drop single-ended DRAM transceiver is implemented in a 0.25 /spl mu/m CMOS process. Digital calibrations are performed for equalization and compensation of data skew and offset voltage. A continuously active on-die termination is used to reduce reflections. A phase detector is proposed for the digital DLL to achieve the S/H time(More)
A delay matrix and a gradual switching of shunt capacitors in delay cells are proposed for a wide-range-locking multi-phase DLL. With an interpolating resistor network, delay step error is greatly reduced by error averaging. The DLL, implemented in 0.13mum CMOS, has a locking range of 40 to 800MHz. With 40 phases, the maximum delay step error is 16.7ps at(More)
An all-digital DLL is designed to generate low jittery 40 phases in a continuous lock range of 110 MHz to 1.4 GHz. The DLL is driven by dual loops-one for phase lock and the other for offset calibration. The two loops are updated by a chopping PD which adaptively extracts valid information for each loop, one at a time. For the optimal 1-bit delay resolution(More)