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A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC
A compact decision-error-tolerant 2b/cycle SAR ADC architecture is presented. Two DACs with different designated functions, SIG-DAC and REF-DAC, are implemented to make the structure compact and toExpand
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A fully-differential capacitive touch controller with input common-mode feedback for symmetric display noise cancellation
TLDR
A fully-differential capacitive touch sensing method is proposed in which common-mode noise currents are symmetrically subtracted at the differential input of the first stage such that it doesn't contribute to dynamic range reduction in the later stages. Expand
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An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement
TLDR
We present a resolution-enhancing design technique for 2b/cycle SAR ADCs with negligible hardware overhead, while relieving the requirements for the aforementioned errors: Reconfiguration of the structure to a normal 1b/ cycle SAR ADC with error-correction capability achieves an 8.6 ENOB from a 9b ADC. Expand
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  • PDF
A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs
TLDR
The conventional register-controlled delay locked loop (RCDLL) with a single delay line requires a complex logic circuit following the phase comparator to prevent the false lock. Expand
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A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme
TLDR
A dual-loop delay-locked loop (DLL) was implemented using an analog voltage-controlled delay line (VCDL) for low jitter. Expand
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A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration
TLDR
A power-efficient and speed-enhancing technique for time-interleaved (TI) SAR ADCs that is assisted by a low-resolution flash ADC is presented. Expand
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26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique
TLDR
In this paper, a multi-step hardware-retirement (MSHR) technique, which disables low-accuracy hardware blocks of scaled sizes with the requirement relaxations from redundancies in an advancement to the reconfiguration scheme in the work of Kong et al. (2013), is reported to alleviate the overhead of additional logic and DACs for ADCs, requiring high resolutions. Expand
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A 1 mW 10-bit 500KSPS SAR A/D converter
TLDR
A 1mW 1.5 V 10-bit 500 KSPS successive approximation (SAR) analog-to-digital converter (ADC) was fabricated in a 0.25 um CMOS technology. Expand
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A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control
TLDR
A 45nm CMOS 7b nonbinary 2b/cycle SAR ADC that operates up to 1GS/s with a 1.25V supply is presented. Expand
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A 10b 150MS/s 123mW 0.18μm CMOS pipelined ADC
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