Hisashi Iwamoto

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Ternary content addressable memory (TCAM) is popular LSI for use in high-throughput forwarding engines on routers. However, the unique structure applied in TCAM consume huge amounts of power, therefore it restricts the applicability to deployment for handling large lookup-table capacity in IP routers. In this paper, we propose a commodity-memory based(More)
Recently, energy consumption of routers has become a serious problem, hence power reduction is an urgent and important challenge. Existing routers always work 100% of their potentials regardless of required performance, such as volume of input traffic. However, semiconductor devices such as lookup logics, buffers, fabrics are not always fully utilized. In(More)
A pre-trained convolutional deep neural network (CNN) is a feed-forward computation perspective, which is widely used for the embedded systems, requires high power-and-area efficiency. This paper realizes a binarized CNN which treats only binary 2-values (+1/-1) for the inputs and the weights. In this case, the multiplier is replaced into an XNOR circuit(More)
In the era of IPv6, since the number of IPv6 addresses rapidly increases and the required speed is more than Giga lookups per second (GLPS), an area-efficient and high-speed IP lookup architecture is desired. This paper shows a parallel index generation unit (IGU) for memorybased IPv6 lookup architecture. To reduce the size of memory in the IGU, we use a(More)
Packet classification has become increasingly complex and important to network equipment intended for future use. A recent trend to achieve complex packet classification is to use software-based methods, which tend to be slower than hardware-based methods. For search, this typically means using ternary content-addressable memory (TCAM) to make(More)
For green networking, Sliced Router Architecture was proposed, which controls the power consumption of routers by adjusting the routers' performance on the basis of the volume of traffic. In this architecture, traffic prediction is used for appropriate power control of router. For obtaining the efficient gain of power reduction, we need to consider the(More)
Dual clock scheme, where master clock (CLKM) and output clock (CLKO) are applied to a SDRAM with different phase, is proposed to achieve very fast access time without area / power penalty. A circuit technique to adjust the different phase between dual clocks is described. This scheme in conjunction with 2-bit prefetch architecture enhances operating clock(More)
Network traffic keeps increasing like as the demand of video streaming. Routers and switches in wire-line networks require guaranteed line rate as high as 20Gbp/s as well as advanced quality of service (QoS). Hybrid SRAM and DRAM architecture previously presented with the benefit of high-speed and high-density requires complex memory management. As a result(More)