Hisanobu Suzuki

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This paper presents a low-power bit-serial Viterbi decoder chip with the code rate r=1/3 and the constraint length K=9 (256 states) for next generation wireless communication applications. The architecture of the add-compare-select (ACS) module is based on the bit-serial arithmetic and implemented with the pass transistor logic circuit. A cluster-based ACS(More)
This paper addresses performance tradeoffs in digit-serial arithmetic architectures for design of dedicated and programmable DSP systems. The advantages and the disadvantages of the digit-serial approach over the bit-parallel approach are discussed in terms of area, latency and power consumption. The addition and the multiplication are chosen for(More)
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