Hiroyuki Mizuno

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In a speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) circuit, the substrate bias is controlled so that delay in the circuit stays constant. Distributions of device speeds are squeezed under fast-operation conditions. With a ring oscillator using 0.25-µm CMOS devices as a test circuit, we found that the worst-case operating frequency was improved(More)
A hierarchical power distribution methodology that enables more than dozen power domains in a chip and a power management scheme using 20 power domains are described. This method can achieve very low leakage current in the partial active mode of a single chip mobile processor. The single chip mobile processor embedded three CPU's that is baseband processor,(More)
Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that(More)
A new computing architecture based on a ground-state search of the Ising model and the probabilistic behavior of a memory cell is proposed. To improve computer performance, a spatial computing architecture that defines an Ising model as the interface between software and hardware is proposed. Various problems can be represented as a spatial parameter in the(More)