Hiroshi Mizuta

  • Citations Per Year
Learn More
Quantum Nanoelectronics Research Centre, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan Department of Electrical and Electronic Engineering, Imperial College London, South Kensington Campus, London SW7 2AZ, U.K. Nokia Research Centre c/o Nanoscience Centre, Cambridge CB30FF, U.K. Nanoscale Systems Integration Group, School of Electronics and(More)
The direct growth of graphene on insulating substrate is highly desirable for the commercial scale integration of graphene due to the potential lower cost and better process control. We report a simple, direct deposition of nanocrystalline graphene (NCG) on insulating substrates via catalyst-free plasma-enhanced chemical vapor deposition at relatively low(More)
The impact of dopant atoms in transistor functionality has significantly changed over the past few decades. In downscaled transistors, discrete dopants with uncontrolled positions and number induce fluctuations in device operation. On the other hand, by gaining access to tunneling through individual dopants, a new type of devices is developed:(More)
The influence of both geometric and offset charge disorder of two-dimensional quantum dot arrays ~also known as network tunnel junctions! on their Coulomb blockade voltage Vb is studied using extensive Monte–Carlo simulations. A general increase of Vb with increasing disorder is confirmed, but an exception to the rule is found for intermediate degrees of(More)
This paper presents a brief review of our recent work investigating a novel bottom-up approach to realize silicon-based nanoelectronics. We discuss fabrication technique, electronic properties, and device applications of silicon nanodots as a building block for various nanoscale silicon devices. r 2006 Published by Elsevier Ltd.
A radio frequency single-electron transistor (RF-SET) based on a silicon-on-insulator (SOI) substrate is demonstrated to operate successfully at temperatures above 4.2 K. The SOI SET was fabricated by inducing lateral constrictions in doped SOI nanowires. The device structure was optimized to overcome the inherent drawback of high resistance with the SOI(More)
We investigate the impact of varying the grain boundary (GB) position on the output (Id–Vd) characteristics of submicron single GB polysilicon thin film transistors (TFTs), by two-dimensional (2D), drift-diffusion based, device simulation. We employ a localized GB trapping model with a distribution of both donor-like and acceptor-like trap states over the(More)
van der Waals (vdW) interactions play a central role in the surface-related physics and chemistry. Tuning of the correlated charge fluctuation in a vdW complex is a plausible way of modulating the molecules interaction at the atomic surface. Here, we report the vdW interaction tunability of the graphene-CO2 complex by combining the first-principles(More)