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We have developed a new technique for generating homogeneously distributed irregular dot patterns useful for optical devices and digital halftoning technologies. To introduce irregularity, we use elaborately designed sequences called low-discrepancy sequences instead of pseudorandom numbers. We also use a molecular-dynamics redistribution method to improve… (More)
A new resonant-tunneling diode with four potential barriers and three quantum wells is fabricated and applied to multiple-valued logic for the first time. The diode exhibited significant double negative resistance characteristics and operated as a triply stable device with a single supply voltage between 180 and 230 K.
The impact of dopant atoms in transistor functionality has significantly changed over the past few decades. In downscaled transistors, discrete dopants with uncontrolled positions and number induce fluctuations in device operation. On the other hand, by gaining access to tunneling through individual dopants, a new type of devices is developed:… (More)
Variable-area resonant tunneling diodes have been fabricated using a process in which the lateral confinement is produced by an in-plane implanted gate. The basic operation of such devices is discussed, and the lateral confinement shown by both measurements and numerical modeling to be very nearly symmetrical about the resonant tunneling diode (RID)… (More)
We investigate the impact of varying the grain boundary (GB) position on the output (I d –V d) characteristics of submicron single GB polysilicon thin film transistors (TFTs), by two-dimensional (2D), drift-diffusion based, device simulation. We employ a localized GB trapping model with a distribution of both donor-like and acceptor-like trap states over… (More)
A simulation model for deep trap states at grain boundaries in Poly-Si TFTs is developed. The model is used for simulation of single GB TFT devices with sub micron channel lengths. The transport physics is clarified and it is found that in short channel devices (L/sub eff/<100 nm) the single GB TFT shows improved subthreshold behaviour compared to its SOI… (More)
Using the notion of discrepancy, we developed a new technique for generating uniformly distributed dot patterns. We designed and prototyped a light guide having prismatic grooves and micro scatterers on the surface. We experimentally confirmed that the new pattern of the micro scatterers effectively prevents moiré patterns, and improves the luminance… (More)
– The Casimir interaction is omnipresent source of forces at small separations between bodies, which is difficult to change by varying external conditions. Here we show that graphene interacting with a metal can have the best known force contrast to the temperature and the Fermi level variations. In the distance range 50–300 nm the force is measurable and… (More)
This paper reports on large area, metal-free deposition of nanocrystalline gra-phene (NCG) directly onto wet thermally oxidized 150 mm silicon substrates using parallel-plate plasma-enhanced chemical vapor deposition. Thickness non-uniformities as low as 13% are achieved over the whole substrate. The cluster size L a of the as-obtained films is determined… (More)
This paper presents a brief review of our recent work investigating a novel bottom-up approach to realize silicon-based nanoelectronics. We discuss fabrication technique, electronic properties, and device applications of silicon nanodots as a building block for various nanoscale silicon devices. r 2006 Published by Elsevier Ltd.