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This paper presents a new model for the statistical analysis of the impact of Random Telegraph Noise (RTN) on circuit delay. This RTN-aware delay model have been developed using Pseudo RTN based on a Markov process with RTN statistical property. We have also measured RTN-induced delay fluctuation using a circuit matrix array fabricated in a 65nm process.(More)
As the minimum feature size shrinks down far below sub-wavelength, Design for Manufacturability or layout regularity plays an important role for maintaining pattern fidelity in photolithography. However, it also incurs overheads in circuit performances due to parasitic capacitance. In this paper, we examine the effect of layout regularity on printability(More)
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