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This¿paper describes an FPGA implementation which features a hardware-oriented Scale Invariant Feature Transform (SIFT) algorithm, a scalable architecture with high-speed mode and high-accuracy mode, and highly parallel datapath modules. The proposed FPGA implementation can generate a SIFT descriptor vector with 50 MHz for VGA resolution¿video¿(640 ×(More)
We have developed a low-power VLSI chip for 60-kWord real-time continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a cache architecture using locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, highly parallel Gaussian Mixture Model (GMM)(More)
This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM, in a 45-nm process and later with large threshold-voltage variation. The proposed voltage-control scheme that improves a write margin and read current, and the write-back scheme that stabilizes unselected cells are applied to the 8T(More)
We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus,(More)
We propose a novel dependable SRAM with 7T memory cells, and introduce a new concept, " quality of a bit (QoB) " for it. The proposed SRAM has three modes: a typical mode, high-speed mode, and dependable mode, in which the QoB is scalable. That is, the area, speed, reliability, and/or power of one-bit information can be controlled. In the typical mode,(More)
SUMMARY This paper proposes a novel dependable SRAM with 7T/14T memory cells, and introduces a new concept, " quality of a bit (QoB) " for it. The proposed SRAM has three modes: a normal mode, high-speed mode, and dependable mode, and dynamically scales its reliability, power and speed by combining two memory cells for one-bit information (i.e. 14 T/bit).(More)
We propose a novel dependable SRAM with 7T cells and their array structure that avoids a half-selection problem. In addition, we introduce a new concept, " quality of a bit (QoB) " for it. The dependable SRAM has three modes (normal mode, high-speed mode, and dependable mode), and dynamically scales its reliability and speed by combining two memory cells(More)
We propose a power management method using a digital voice activity detection (VAD) module for intelligent ubiquitous sensor systems. When this VAD module detects a speech signal, a main signal processing circuit is connected to a power source. When no speech signal is detected, most circuits except VAD are blocked off, thereby reducing stand-by power for(More)