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— This paper describes an FPGA implementation which features a hardware-oriented Scale Invariant Feature Transform (SIFT) algorithm, a scalable architecture with high-speed mode and high-accuracy mode, and highly parallel datapath modules. The proposed FPGA implementation can generate a SIFT descriptor vector with 50 MHz for VGA resolution video (640 × 480(More)
We propose a GMM processor for large vocabulary real-time continuous speech recognition. This processor achieves low operating frequency and low memory bandwidth using parallelization and vector look-ahead schemes, which are suitable to FPGA implementation. We designed the proposed processor on a Celoxica RC250 FPGA board, and confirmed that the required(More)
This paper describes a proposal of non-volatile cache architecture utilizing novel DRAM/MRAM cell-level hybrid structured memory (D-MRAM) that enables effective power reduction for high performance mobile SoCs without area overhead. Here, the key point to reduce active power is intermittent refresh process for the DRAM-mode. D-MRAM has advantage to reduce(More)
This paper demonstrates that an 8T memory cell can be alternative design to a 6T cell in a future highly-integrated SRAM, in a 45-nm process and later with large threshold-voltage variation. The proposed voltage-control scheme that improves a write margin and read current, and the write-back scheme that stabilizes unselected cells are applied to the 8T(More)
We propose a novel dependable SRAM with 7T memory cells, and introduce a new concept, " quality of a bit (QoB) " for it. The proposed SRAM has three modes: a typical mode, high-speed mode, and dependable mode, in which the QoB is scalable. That is, the area, speed, reliability, and/or power of one-bit information can be controlled. In the typical mode,(More)
SUMMARY This paper proposes a novel dependable SRAM with 7T/14T memory cells, and introduces a new concept, " quality of a bit (QoB) " for it. The proposed SRAM has three modes: a normal mode, high-speed mode, and dependable mode, and dynamically scales its reliability, power and speed by combining two memory cells for one-bit information (i.e. 14 T/bit).(More)
We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus,(More)
In this study, 12 healthy males were exposed to various light conditions (2300K, 3000K, 5000K and dim) for 1.5h at midnight. The conditions of 3000K and 5000K were created by commercial fluorescent lamps. The light at 2300K was achieved by fitting a 3000K fluorescent lamp with a special filter that absorbed short-wavelength light. The vertical illuminance(More)