Hiroki Noguchi

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This¿paper describes an FPGA implementation which features a hardware-oriented Scale Invariant Feature Transform (SIFT) algorithm, a scalable architecture with high-speed mode and high-accuracy mode, and highly parallel datapath modules. The proposed FPGA implementation can generate a SIFT descriptor vector with 50 MHz for VGA resolution¿video¿(640 ×(More)
We propose a low-power non-precharge-type two-port SRAM for video processing. The proposed memory cell (MC) has ten transistors (10T), comprised of the conventional 6T MC, a readout inverter and a transmission gate for a read port. Since the readout inverter fully charges/discharges a read bitline, there is no precharge circuit on the read bitline. Thus,(More)
We propose a novel dependable SRAM with 7T memory cells, and introduce a new concept, “quality of a bit (QoB)” for it. The proposed SRAM has three modes: a typical mode, high-speed mode, and dependable mode, in which the QoB is scalable. That is, the area, speed, reliability, and/or power of one-bit information can be controlled. In the typical mode,(More)
We have developed a low-power VLSI chip for 60-kWord real-time continuous speech recognition based on a context-dependent Hidden Markov Model (HMM). Our implementation includes a cache architecture using locality of speech recognition, beam pruning using a dynamic threshold, two-stage language model searching, highly parallel Gaussian Mixture Model (GMM)(More)
This paper proposes a novel dependable SRAM with 7T/14T memory cells, and introduces a new concept, “quality of a bit (QoB)” for it. The proposed SRAM has three modes: a normal mode, highspeed mode, and dependable mode, and dynamically scales its reliability, power and speed by combining two memory cells for one-bit information (i.e. 14 T/bit). By carrying(More)
We propose a low-power two-port SRAM for real-time video processing that exploits statistical similarity in images. To minimize the discharge power on a read bitline, a majority-logic circuit decides if input data should be inverted in a write cycle, so that “1”s are in the majority. In addition, for further power reduction, write-in data are reordered into(More)
We propose a GMM processor for large vocabulary real-time continuous speech recognition. This processor achieves low operating frequency and low memory bandwidth using parallelization and vector look-ahead schemes, which are suitable to FPGA implementation. We designed the proposed processor on a Celoxica RC250 FPGA board, and confirmed that the required(More)
This paper describes a SIFT (Scale Invariant Feature Transform) descriptor generation engine which features a VLSI oriented SIFT algorithm, three-stage pipelined architecture and novel systolic array architectures for Gaussian filtering and key-point extraction. The ROIbased scheme has been employed for the VLSI oriented algorithm. The novel systolic array(More)