Hirofumi Shinohara

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6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (/spl sigma//sub v/spl I.bar/Local/). To achieve high-yield SRAM arrays in presence of random /spl sigma//sub v/spl I.bar/Local/ component, we propose worst-case analysis that determines the boundary of the stable Vth region(More)
In this paper, a closed-form expression for estimating a minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic gates is proposed. V<sub>DDmin</sub> is defined as the minimum supply voltage at which circuits can operate correctly. V<sub>DDmin</sub> of combinational circuits can be written as a linear function of the square-root of logarithm of the(More)
A 32-bit CPU which operates with the lowest energy of 13.4 pJ/cycle at 0.35V and 14MHz, operates at 0.22V to 1.2V and with 0.14µA sleep current is demonstrated. The low power performance is attained by Reverse-Body-Bias-Assisted 65nm SOTB CMOS (Silicon On Thin Buried oxide) technology. The CPU can operate more than 100 years with 610mAH Li battery. Extended(More)
Error Detection FFs for Dynamic Voltage Scaling (DVS) has been proposed. This technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. The error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the(More)