Hiroaki Shikano

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1. Abstract This paper describes processing performance of MP3 audio encoding on a heterogeneous chip multiprocessor (HCMP) that possesses different types of processing elements (PEs) such as general-purpose processors and special-purpose processors. The HCMP realizes higher performance than conventional single-core processors or even homogeneous(More)
The next-generation cloud computing systems are expected to be connected to the real world more tightly by massive amounts of sensors and actuators. Today's clouds, however, are not capable of handling massive sensor data or giving fast feedback to the real world because of the long latency and limited bandwidth of WANs. We propose a cloud architecture that(More)
With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten development period and reduce the power consumption. To this end, the compiler for a multi core processor is expected not only to parallelize program effectively, but also to control the(More)
A heterogeneous multi-core processor (HMCP) architecture, which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption with the support of a parallelizing compiler, was developed. The evaluation was performed using an MP3 audio encoder on a simulator that accurately models the HMCP. It(More)
Heterogeneous multicore architectures integrating several kinds of accelerator cores in addition to general purpose processor cores have been attracting much attention to realize high performance with low power consumption. To attain effective high performance, high application software productivity, and low power consumption on heterogeneous multicores,(More)
With the advance of semiconductor technology, chip multiprocessor architectures, or multi core processor architectures have attracted much attention to achieve low power consumption, high effective performance, good cost performance and short hardware/software development period. To this end, parallelizing compilers for chip multiprocessors are expected(More)
Multicore processors, or chip multiprocessors, which allow us to realize low power consumption, high effective performance, good cost performance and short hardware/software development period, are attracting much attention. In order to achieve full potential of multicore processors, cooperation with a parallelizing compiler is very important. The latest(More)
Chip multi-processors (CMP) have attracted much attention since they achieve higher performance not by raising operating frequency but by utilizing a number of transistors in parallel. However, simply increasing the number of processor elements (PE) will result in raising power consumption. This work presents a power-aware compiler controllable(More)
Datacenters are now widely used, and their sizes are increasing due to the rapid spread of cloud computing. Meanwhile, the cost of IT-system operations occupies 60% of the total cost in a datacenter. So far, improving operations has been focused on automating operations with operation management middleware. However, designing operational procedures,(More)
The main objective of this work is to design a memory cell in Field Programmable Gate Array (FPGA) that consumes lesser power with reduced delay constraint. In the existing system, the FPGA is based on 10T Static Random Access Memory (SRAM) cell configuration in which power consumption is relatively high. The proposed work includes a Self controllable(More)