Hesham A. Al-Twaijry

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In recent years computer applications have increased in their computational complexity. The industry-wide usage of performance benchmarks, such as SPECmarks, and the popularity of 3D graphics applications forces processor designers to pay particular attention to implementation of the floating point unit, or FPU. This paper presents results of the Stanford(More)
Booth encoding is a method of reducing the number of summands required to produce the multiplication result. This paper compares the performance/area tradeoos for the diierent Booth algorithms when trees are used as the summation network. This paper shows that the simple non-Booth algorithm is not a viable design, and that currently Booth 2 is the best(More)
SNAP-The Stanford Sub-nanosecond arithmetic processor is an inter-disciplinary eeort to develop validated theory, and tools for realizing an arithmetic processor with execution rates under 1ns. The project has targeted the full spectrum of tradeoos from algorithms, circuit optimizations, system issues, and development o f metrics to characterize processors.