Her-Ming Jong

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This paper describes fully pipelined parallel architectures for the 3-step search block-matching motion estimation algorithm. Difficulties of this algorithm in hardware implementation were overcomed by use of intelligent d a ta arrangement and memory configuration. Techniques for reducing interconnections and external memory accesses were also develope’d.(More)
A tree-structure based architecture for vector quantization (VQ) is proposed and implemented by VLSI in this paper. The proposed folded-tree architecture is designed by 0.8 m CMOS VLSI technology. The die size is 4.65 5.21 mm 2 and estimated clock rate is about 34MHz, which satis es most real-time applications. Since it is basically a mean squared error(More)
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