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This paper presents a general architecture for soft processors based on a modified Harvard architecture, SHARF. The separation of instruction and data path is extended by the concept of splitting application and control (address) specific computations. ALUs with any kind of operations and data types can be designed for a SHARF specific controller.(More)
In this paper, we present the architecture of a coarse-grain reconfigurable cell designed for pipelined arithmetic computing applications. We apply the concept of separation between control-path and computation-path logic in the so-called reconfigurable coprocessor array architecture. Variations of the cells are implemented on CMOS 0.35 and 0.13(More)
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