Helmut Puchner

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Multi-bit upset (MBU) events collected from accelerated soft error rate (SER) measurements performed with a quasi-monoenergetic neutron beam were analyzed with a threefold purpose. The first goal was to qualitatively assess the applicability and effectiveness of single-bit Error Detection And Correction algorithms and circuits (EDAC). The second goal was to(More)
In previous works, we have demonstrated the importance of dynamic mode testing of SRAM components under ionizing radiation. Several types of failures are difficult to expose when the device is tested under static (retention) mode. With the purpose of exploring and defining the most complete testing procedures and reveal the potential hazardous behaviors of(More)
While single bit upsets on memories and storage elements are mitigated with either the use of redundancy and/or error correction codes, Multiple-Cell-Upsets (MCU) may become a significant threat to the integrity of systems when the corrupted cells belong to the same word. In this paper, we identify four types of MCUs as they were recorded during several(More)
We present a comprehensive review of design as well as process options to completely eliminate soft error induced single event latchup (SEL) in modern CMOS based SRAM technologies under datasheet operating conditions. The detailed mechanism of latchup under radiation environment is discussed and analyzed. EPI substrate starting material and the use of a(More)
Source and drain junction capacitance has been varied by utilizing different implant conditions for the MOSFETs to explore the possibility of improving SEU (single event upset) immunity of SRAM cells. It is found. that the junction capacitances of both the n/sup +//p-well and p/sup +//n-well can vary in a wide range. The resulting SEU FIT (failure in time)(More)
The predictive simulation of the formation of voids in interconnect lines is important for improving capacitance and timing in current memory cells. The cells considered are used in wireless applications such as cell phones, pagers, radios, handheld games, and GPS systems. In backend processes for memory cells, ild (interlayer dielectric) materials and(More)
Application of the EKV3.0 model to 0.15mum CMOS technology with single poly, and buried channel PMOS, is presented with emphasis on scaling properties of the technology and the model. The EKV3.0 model is illustrated for its fit to NMOS and PMOS drain current, transconductances and output characteristics in weak, moderate and strong inversion over a large(More)
A triple-well scheme has been implemented on an 18-Mb fast synchronous SRAM by using a high energy implant to evaluate its impact on the alpha-particle-induced accelerated soft error rate (ASER). The device uses a single poly 0.15-/spl mu/m CMOS process. The SER FIT rates have been measured from silicon with and without the triple well. In contrast to the(More)
A single poly, 0.15 /spl mu/m process has been modified to fabricate a 18 Mb fast synchronous memory for evaluation of the process impact on the a-particle SEU (single Event Upset) performance. The process options include (1)increasing the source/drain junction capacitance, (2)adding a backend capacitor between the storage nodes, and (3)using the epitaxial(More)