Helder F. de A. Oliveira

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Design complex embedded systems demands method and tools that allow the simulation and verification in an efficient and practical way. This paper proposes the development and evaluation of a distributed simulation platform of heterogeneous simulators based on High Level Architecture (HLA), a middleware for distributed discrete event simulation, in order to(More)
Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different parts of a complex design, functional verification becomes a challenge. Lately, the verification process of this technique has been executed in a Register-Transfer Level (RTL) abstraction, based on the Common Power Format (CPF) and(More)
Power consumption is a big challenge in chip design. Decisions taken in early design phases have large impact on the power consumption. Generally, simulation-based Design Space Exploration (DSE) is computationally costly for large problems due the size of design space. Simulate the possible scenarios in a distributed fashion can decrease the time to find(More)
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