Heinz Hoenigschmid

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Memory interfaces for high-speed graphics systems have reached the 4 to 6 Gb/s/pin regime with GDDR4 and the introduction of GDDR5 [1-4] at chip densities up to 512Mb. To satisfy the demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. In this paper, a 7Gb/s/pin 1Gb GDDR5 DRAM with an array(More)
A BSIM3v3 based ferroelectric memory field effect transistor (FEMFET) compact model for circuit simulation is presented. Its analytical approach is based on the MOS capacitor equations taking into account the influence of a ferroelectric polarization. The hysteresis behavior of the gate ferroelectric has been modeled by using the distribution function(More)
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