Heiko Hinkelmann

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A compact chip identification (ID) circuit with improved reliability is presented. Ring oscillators are used to measure the spatial process variation and the ID is based on their relative speeds. A novel averaging and postprocessing scheme is employed to accurately determine the faster of two similar-frequency ring oscillators in the presence of noise.(More)
Efficient cycle-based reconfiguration of datapaths can be realized on current FPGAs by designing merged datapaths, which can execute different tasks depending on the datapath control. In our previous work, we provided a synthesis tool for the automated generation of such datapaths. The objective in this paper is a reduction of the resource requirements for(More)
We explore the design of a coarse-grained reconfigurable architecture for wireless sensor network nodes, which combines high energy efficiency with programmability and hence meets the requirements of small energy-constraint embedded systems. Its energy consumption, area, and performance are evaluated and compared to processor and ASIC architectures. Our(More)
We describe the application of a hybrid functional level power analysis (FLPA) and instruction level power analysis (ILPA) approach to a processor model implemented on an FPGA. This technique enables the estimation of the task specific power consumption of the modeled processor, in our case a LEON2, very early during a system design flow, based on the(More)
Increasing power consumption and growing design effort are considered limiting factors in the design of chip-wide synchronous System-on-Chip designs. The attempt to get over these problems leads to an intensified look at asynchronous communication solutions, sometimes based on Network-on-Chips. Despite this basically asynchronous approach, most of the(More)
In this paper, we present a methodology for rapid prototyping of wireless sensor networks that allows to embed sophisticated debugging functionality in a mote prototype and thereby monitor entire networks. We achieve this goal by combining two fundamental concepts: the use of a reconfigurable sensor node prototype platform, and an auxiliary network(More)
Reconfigurable hardware is often used in an attempt to boost performance of an embedded system while minimizing the cost penalty of additional hardware. The key method applied to achieve this goal is the re-use of hardware resources for different tasks. However, reconfigurable systems tend to have a large internal state, which complicates rapid task(More)