Heechun Park

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In through-silicon-via (TSV) based 3-D integrated chips (ICs), synthesizing 3-D clock tree is one of the most challenging tasks. Since the clock signal is delivered to clock sinks (e.g., latches, flip-flops) through TSVs, any fault on a TSV in the clock tree may cause a chip failure. Therefore, ensuring the reliability of clock TSVs in 3-D ICs is highly(More)
Recently, to cope with clock TSV (Through-Silicon-Via) reliability problem efficiently, a new circuit structure called TSV Fault-tolerant Unit (TFU) and the allocation method of TFUs have been proposed. However, the existing design methods partially or never addressed following key issues: (1) <i>the feasibility of TSV pairing for TFU allocation</i>, (2)(More)
This work proposes a new method of synthesizing asynchronous circuits targeting its practical usability. The key contribution of this work is finding an effective technique of inter-mixing the two design principles namely handshaking based single-rail and timing annotated (i.e., delay insensitive) dual-rail of asynchronous circuits. Precisely, we propose(More)
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