Hee-Sung Kang

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A 0.25m, four-layer-metal, 1.5-V, 600-MHz, fully depleted (FD) silicon-on-insulator (SOI) CMOS 64-bit ALPHA1 microprocessor integrating 9.66 million transistors on a 209-mm silicon die has been developed leveraging the existing bulk design. FD-SOI technology is used because it has better immunity for dynamic leakage current than partially depleted SOI in(More)
We have fabricated normally-off two different GaN MOSFETs with Al<sub>2</sub>O<sub>3</sub> gate insulator with thickness of 38- and 54-nm and investigated the difference in device performance. From the C-V measurement, relatively higher threshold voltage and smaller threshold voltage shift were observed in the device with 54-nm-thick(More)
We have investigated and proposed a highly scaled tunneling field-effect transistor (TFET) based on Ge/GaAs heterojunction with a drain overlap to suppress drain-induced barrier thinning (DIBT) and improve low-power (LP) performance. The highly scaled TFET with a drain overlap achieves lower leakage tunneling current because of the decrease in tunneling(More)
The AlGaN/GaN nanowire omega-shaped-gate FinFET have been successfully fabricated demonstrating much improved performance compared to conventional AlGaN/GaN MISHFET. The AlGaN/GaN omega-shaped-gate FinFET exhibited the remarkable on-state performances, such as maximum drain current of 1.1 A/mm, low on-resistance, and low current collapse compared to that of(More)
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