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Corynebacterium glutamicum ATCC13032 and Brevibacterium flavum JV16 were engineered for l-valine production by over-expressing ilvEBN r C genes at 31 °C in 72 h fermentation. Different strategies were carried out to reduce the by-products’ accumulation in l-valine fermentation and also to increase the availability of precursor for l-valine biosynthesis. The(More)
Three-dimensional (3D) integration and multi-level cell (MLC) are two attractive technologies to achieve ultra-high density for mass storage applications. In this work, a three-layer 3D vertical AlOδ/Ta2O5-x/TaOy resistive random access memories were fabricated and characterized. The vertical cells in three layers show good uniformity and high performance(More)
Brevibacterium flavum ATCC14067 was engineered for l-valine production by overexpression of different ilv genes; the ilvEBNrC genes from B. flavum NV128 provided the best candidate for l-valine production. In traditional fermentation, l-valine production reached 30.08 ± 0.92 g/L at 31°C in 72 h with a low conversion efficiency of 0.129 g/g. To further(More)
It becomes more and more important to protect the security of web sites. In order to solve the problem about web site disaster recovery, a web site protection oriented remote backup and recovery method is proposed in this paper. Customers can design various backup strategies such as full, incremental and differential backup by themselves. A multi version(More)
A 24-GHz fully integrated integer-N phase-locked loop (PLL) is presented in this paper. Benefiting from the bias noise filtering technique, the voltage controlled oscillator (VCO) in the loop achieves a low phase noise. Moreover, the supply voltage of VCO is as low as 0.8-V due to the low-threshold-voltage transistors used in the design. The proposed PLL is(More)
Coplanar waveguides (CPW) are promising candidates for high quality passive devices in millimeter-wave frequency bands. In this paper, CPW transmission lines with and without ground shields have been designed and fabricated on 65nm CMOS technology. A physical-based model is proposed to describe the frequency-dependent per-unit-length L, C, R, and G(More)
The design flow of a lumped Elements varactor-loaded Transmission-Line phase shifter (VLTL) is illustrated and a 60GHz phase shifter of this kind is implemented in IBM 90nm CMOS process in this paper. The proposed VLTL is area-saving, occupying only 937um × 110um as it uses inductors instead of long transmission lines. This phase shifter is digitally(More)