Hazar Yueksel

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The implementation of a digital four-level pulseamplitude-modulation reduced-state sliding-block Viterbi detector (VD) with two substates and two embedded per-survivor decision-feedback taps operating at one-eighth of the modulation rate is described. Implemented in an experimental chip fabricated in 14 nm CMOS, the VD is designed to recover data at 25.6(More)
High-speed SAR ADCs became popular with modern CMOS technologies because of their mostly digital logic, making them highly suitable for compact and powerefficient multi-GS/s time-interleaved ADCs. As many applications cannot tolerate input swings ≥1Vppd, comparator noise limits the SNDR of SAR ADCs, making gain stages necessary for higher SNDR – either as(More)
We investigate the impact of synchronization and survivor path memory lengths on latency and the error rate of a sliding-block receiver that implements the Viterbi algorithm for high-speed data transmission over dispersive channels. All of the previous work on Viterbi detection has assumed that the synchronization length equals the survivor path memory(More)
The implementation of a 64x time-interleaved ADC in 32nm CMOS SOI is analyzed. Measurement results confirm 33 dB SNDR up to 19.9 GHz at 90 GS/s and 1.2V supply. Architecture details and analysis show insights into limitations and potentials of the chosen architecture. In par-ticular the input bandwidth is of concern for ADCs at more than 64 GS/s, as a(More)
A high-performance low-latency transmission system based on a concatenated code consisting of inner four-dimensional five-level pulse-amplitude-modulation (5-PAM) trellis-coded modulation and an outer Reed-Solomon (RS) code is proposed for a high-speed data link over time-dispersive channels. The implementation of high-speed sequence detection in(More)