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Creation of large FPGAs needs radical efficient changes in architecture to improve speed, density and software mapping time. Based on industry experience with standard ASICs, we believe that partitioning and hierarchy become an obligation for FPGA hardware and software developments. As an alternative we propose a new Multilevel hierarchical FPGA (MFPGA)(More)
This paper presents an improved interconnect network for Tree-based FPGA architecture that unifies two unidirec-tional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the(More)
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butter y-Fat-Tree topology, and an upward network using hierarchy. Studies based on Rent's Rule show that switch requirements in this architecture grow slower than in traditional Mesh topologies. New(More)
We present a routability-driven top-down clustering technique for area and power reduction in clustered FPGAs. This technique is based on a multilevel partitioning approach. It leads to better device utilization, savings in area, and reduction in power consumption. Routing area reduction of 15% is achieved over previously published results. Power(More)
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-Fat-Tree topology, and an upward network using hierarchy. Studies based on the Rent's Rule show that wiring and switch requirements in the MFPGA grow slower than in(More)
In this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is implemented as an MFPGA tree network [6]. Unlike previous clustered mesh architectures, the mesh of tree allows us to consider large clusters sizes (thanks to MFPGA depopu-lated local interconnect). Experimentation shows that we obtain a reduction of 14%(More)
In this paper we present the effect of lookup table (LUT)size (no of inputs to a LUT) and cluster size (no of LUTs per cluster) on the area and critical path of a tree based FPGA architecture (MFPGA). For this purpose we have designed a flow that places and routes a set of bench mark circuits on different tree based architectures with varying lookup table(More)
In this paper we evaluate a new multilevel hierarchical MFPGA. The specific architecture includes two unidirectional programmable networks. A downward network based on the butterfly-fat-tree topology, and a special rising network. New tools are developed to place and route several benchmark circuits on this architecture. Comparison with the traditional(More)
In this paper we present a new Mesh of Tree FPGA architecture , where clusters are surrounded by a Mesh style interconnect and each cluster local interconnect is equivalent to a depopulated Tree-based topology. The particularity of the architecture allows to retain the distinction between Mesh and Tree levels in the mapping phase. This has an important(More)