Hayder Al-Khalissi

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—To simplify program development for the Single-chip Cloud Computer (SCC) it is desirable to have high-level, shared memory-based parallel programming abstractions (e.g., OpenMP-like programming model). Central to any similar programming model are barrier synchronization primitives, to coordinate the work of parallel threads. To allow high-level barrier(More)
The continuous increase of the number of processing cores on die poses a new set of challenges to HPC applications programming including how to model, write, and verify software that has to use the full power of NoC-based manycore processors. Therefore, to simplify program development for the Single-chip Cloud Computer (SCC), it is desirable to have(More)
Several recent manycores leverage a hierarchical design, where small-medium numbers of cores are grouped inside clusters and enjoy low-latency, high-bandwidth local communication through fast L1 scratchpad memories. Several clusters can be interconnected through a network-on-chip (NoC), which ensures system scalability but introduces non-uniform memory(More)
The advent of the Single-chip Cloud Computer (SCC) chip in the many-core realm imposes challenges to programmers. From a programmer's perspective is desirable to use the shared memory paradigm, employing high-level parallel programming abstractions such as OpenMP. In this paper we discuss our ongoing efforts to support OpenMP on SCC. Specifically, we focus(More)
This paper proposes an effective barrier synchronization implementations for shared memory-based parallel programming models (e.g. OpenMP) on the Intel SCC non-cache- coherent platform. Barrier synchronization primitives are key components of these programming models to coordinate the parallel threads. Therefore, we need an efficient implementation of the(More)
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