Haydar Saaied

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In this paper, we suggest an adaptive approach for the Clock Distribution Network (CDN) to cope with a modification in the VLSI system design. The CDN's wires are adjusted iteratively to reduce the skew that is resulting from a minor modification in the clock pins of a complex VLSI system. Such skew can be remedied by selecting a Balancing Node (BN) and(More)
The need for incremental algorithms to implement engineering changes (ECs) in clock trees (CTs) is critical in the system-on-a-chip (SoC) design cycle. An algorithm, called adaptive wire adjustment (AWA), is proposed to minimize the clock skew iteratively to any given bound. In order to speed up AWA's convergence, a local topology-modification (LTM)(More)
Design of clock distribution networks (CDNs) in SoCs is one of the critical aspects in the realization of high performance products. Traditionally, the CDNs are generated based on binary tree data structure. However, this approach has it own limitations in terms of silicon utilization, power dissipation and latency. In this paper we propose to migrate to a(More)
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