This paper presents a time-efficient 4-bits carry select adder (CSA) using the arithmetic A2 redundant binary representation. This structure is very suitable for implementation in VLSI of simple mixed-signal neural networks with on-chip learning. This adder is based on a classical weighted binary carry-select adder with two input/output trans-coders.… (More)
A power-efficient 8-bits digital adder using the new arithmetic A2 redundant binary representation is presented.
The main goal of our work is to investigate the delay performances of redundant binary arithmetic operators using different CMOS logic and mixed signals styles. This paper presents a novel technique for A2 redundant binary multiplication in mixed-signal circuits especially for neural networks applications. The proposed multiplier consists of three cascaded… (More)