Hassan Faraji Baghtash

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in this paper is proposed a novel atto-ampere current mirror (AACM) which reaches the minimum yet reported current range of 0.4aA. Operation of this circuit is based on source voltage modulation instead of conventionally used gate voltage modulation which interestingly prevents usage of commonly required voltage shifting in those circuits. The proposed(More)
In this paper a novel ultra-high compliance, low power, very accurate and high output impedance current mirror/source is proposed. Deliberately composed elements and a good combination (for a mutual auto control action) of negative and positive feedbacks in the proposed circuit made it unique in gathering ultra-high compliances, high output impedance and(More)
⎯A novel CMOS atto-ampere current mirror (AACM) is proposed which reaches the minimum yet reported current range of 0.4 aA. Operation of this circuit is based on the source voltage modulation instead of the conventionally used gate voltage modulation which interestingly prevents usage of commonly required voltage shifting in those circuits. The proposed(More)
An ultra-wideband low noise amplifier is presented in this paper. The current-reuse technique is used to get the desired results with lower power consumption. Input impedance matching of 50 Ω is provided by a common-gate through resistive feedthrough stage all-entire the 3-11GHz band of interest. Second stage is used to get a good flatness and high(More)
This paper exhibits an examination, configuration, design to measure nonlinear characteristics of low noise amplifier(LNA) furthermore investigation, assess those estimations in the AWR microwave office Tool. A large portion of the critical aspects of LNA will be in linear measurements and which is composed, designed and simulated for the ultra LNA from(More)
A variable-gain amplifier with very low power consumption and wide tuning range is presented. The operational principle of this unique structure is discussed, its most important formulas are derived and its outstanding performance is verified by simulation in TSMC 0.18-μm N-well CMOS fabrication process. Owing to the novel zero-pole repositioning technique,(More)
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