Haroon-Ur-Rashid Khan

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This paper evaluates the Triplet Based Architecture, TriBA – a new idea in chip multiprocessor architectures and a class of Direct Interconnection Network (DIN). TriBA consists of a 2D grid of small, programmable processing units, each physically connected to its three neighbors so that advantageous features of group locality can be fully and efficiently(More)
This paper presents a flexible two-layer buffer caching scheme to improve the performance of storage cache which is used to serve multiple concurrently accessing applications with diverse access patterns. To achieve this, the proposed scheme dynamically partitions the cache among applications. At the first layer, it uses a configurable global cache(More)
We have entered the era of many-core processors and complex SoCs, where on-chip interconnection networks play a dominant role in determining the performance, power, and ultimately cost of a system. Therefore, interconnection strategy that supports efficient communication between IP blocks is essential. Any communication model can be well characterized by(More)
Image compression scheme is divided into different operational phases for reliable, successful and efficient results. In this paper, layered scalable concurrent image compression ISCIC pre coder is analyzed which is already proved scalable and stable with respect to data transmission and pixel loss. In the light of available compression schemes associated(More)
Any communication model can be well characterized by locality properties and, any topology has its intrinsic, structural, locality characteristics. Spatial locality of processing cores in a multi-core chip can be exploited to gain computational efficiency of a network on chip. In this paper we propose a new criterion in performance evaluation of NoC(More)
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