Haripriya Janardhan

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A digital phase-locked loop (DPLL) is designed and is shown to have 1GHz operation with lock time of 643.36ns. The lock time was reduced by adjusting the charge pump current and the loop filter capacitor. There was a trade-off between the lock time, loop filter capacitor, and ripples on the output of the VCO. Design procedures and simulation results are(More)
A five stage current starved Voltage Controlled Oscillator (CMOS VCO) is designed in this paper. The design is implemented in Tanner environment with high oscillation frequency and low power consumption. Oscillation frequency of the designed VCO ranges from 25.70 MHz to 222.53 MHz. The circuit is simulated using 180nm SCN018 Technology. Simulation results(More)
Obtaining accurate data in any system is a challenging problem. Multi-sensor data fusion is a widely used technique to improve the accuracy. In this paper, measurement level fusion, covariance union fusion, and state vector fusion based on Kalman filters for systems with delayed states is presented. The obtained Kalman filter based data fusion algorithms(More)
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