Harikrishnan Ramiah

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A new perturbation method, called Hierarchical-Congregated Ant System (H-CAS) has been proposed to perform the variable-order bottom-up placement for VLSI. H-CAS exploits the concept of ant colonies, where each ant will generate the perturbation based on differences in dimensions of the VLSI modules in hard modules floorplanning and differences in area of(More)
A low-power, low-phase noise, high tuning range, and fully integrated inductorless RC-VCO (voltage-controlled oscillator) for OC-48 application is designed and simulated in standard 0.18 µm CMOS technology. The proposed inductorless RC-VCO has a simulated phase noise of-141 dBc/Hz at 1 MHz offset from the carrier frequency of 2.4 GHz, with a bias current of(More)
This paper presents an ultra-low voltage and low power current bleeding CMOS double balanced mixer targeted for ZigBee application in 2.4 GHz frequency band. It introduces and discusses a modified CMOS based current bleeding mixer topology adopting a combination of NMOS current bleeding transistor, with a PMOS Local Oscillator (LO) switching stage and(More)
Floorplanning is crucial in VLSI chip design as it determines the time-to-market and the quality of the product. In this work, Variable-Order Ant System (VOAS) is developed and combined with a floorplan model namely Corner List (CL) to optimize the area and wirelength. CL is used to represent the floorplan layout. Although CL has proven to have the same(More)
The advent of technology with the increasing use of wireless network has led to the development of Wireless Body Area Network (WBAN) to continuously monitor the change of physiological data in a cost efficient manner. As numerous researches on wave propagation characterization have been done in intrabody communication, this study has given emphasis on the(More)
—Precise modeling of radio propagation is necessary for experiencing the benefits of wireless technology for indoor environments. Among many modeling techniques, the ray tracing based prediction models become popular for indoor wireless radio propagation characterization. Though the ray tracing models are popular, their key deficiency is the slower(More)
For the first time, a new circuit to extend the linear operation bandwidth of a LTE (Long Term Evolution) power amplifier, while delivering a high efficiency is implemented in less than 1 mm2 chip area. The 950 µm × 900 µm monolithic microwave integrated circuit (MMIC) power amplifier (PA) is fabricated in a 2 µm InGaP/GaAs process. An on-chip analog(More)
A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT(More)