Harihara Indana

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This paper presents a method to model the drain current of LDMOS working in the 3<sup>rd</sup> quadrant (Vds&lt;;0), which is important for power management IC design. The DIBL effect in 3<sup>rd</sup> quadrant is shown to be much more significant than that in 1<sup>st</sup> quadrant (Vds&gt;0), and is not captured by the existing LDMOS models. Also, the(More)
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